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CERES Simulator Images

Simulator Information   /  Images

Image: CERES Simulator The bare circuit cards were first fitted with sockets to facilitate chip replaceability and the use of daughter boards to allow the use of inexpensive commercial grade non-flight SRAM and EPROM memory chips. Then the cards were fitted into an electronic enclosure large enough to hold the whole embedded processor flight electronics system.
Image: CERES Simulator The interconnections between the two supporting personal computers and the embedded flight processors were then made using commercially available I/O cards. The EPROMS were loaded with the TRW/CERES flight code, the CERES gimbal engineering models were converted into executable PC software and the TRW ground support software was installed on the PC used for a system monitor.
Image: CERES Simulator The entire system was then checked and then powered-up with a logic analyzer connected to the processors to observe that instructions were executing properly. Both processors perform a main loop cycle every 10 milliseconds, but are synchronized with each other. The simulation processors respond as if they were controlling real CERES hardware since the virtual instrument PC is fast enough to send back results from the engineering models. The processors execute all CERES elevation and azimuth scan modes as designed.
Image: CERES Simulator This photo shows the TRMM CERES Instrument Simulator in operation. The PC status screen on the left is the virtual instrument which gives real-time commanded elevation and azimuth position data. The PC screen on the right is the TRW Bench Checkout Unit which serves as a monitor for the simulator and displays important engineering parameters of the CERES system.
Image: CERES Simulator This photo shows the CERES Simulator in operation. The enclosure on the left contains the TRW-designed flight electronics consisting of twin 80C186 microprocessors and unmodified Flight Code contained in EPROMS. The embedded flight electronics are linked to the BCU PC by shared memory and to the Virtual Instrument PC by fast parallel I/O cards. Memory uploads consisting of either Long or Short commands or command sequences can be tested and validated with the CERES Simulator. TRW designed the flight electronics cards and associated microprocessor flight code. TRW/NASA developed the engineering models of the elevation and azimuth gimbals used in the virtual instrument. CSC - Jim Donaldson and Chris Slominski provided assistance to integrate and link the embedded processors to the virtual instrument PC, tuning the system to a functional real-time CERES Instrument Simulation System. NYMA - Bryant D. Taylor provided electronics hardware assistance to assemble, interconnect and de-bug the mircoprocessors and I/O cards.
Image: CERES Simulator The circuit card in the top left-hand side is the Spacecraft Interface card which links the embedded processors of the simulator to the PC monitor. The card on the lower right-hand side is the Instrument Control Processor (ICP) which contains a socketed 80C186 microprocessor and EPROMS loaded with TRW/CERES flight code, identical to the orbiting satellite software. The ICP is also linked to the virtual instrument PC thru the digital interface card, located top-right.
  Image: NASA Logo NASA Official: Dr. Norman Loeb
Page Curator: Edward Kizer
Page Last Modified: 10/16/2017 11:04:57 EST
Site Last Modified: 11/07/2017 17:18:43 EST